BY COMFORT OGBONNA
Huawei Technologies has unveiled a new chip design approach that shifts focus away from traditional transistor miniaturization and instead prioritizes faster internal data transmission across chips and computing systems, a move it says could help China advance semiconductor capabilities despite ongoing U.S. export restrictions.
The strategy comes at a time when China remains cut off from accessing the most advanced extreme ultraviolet lithography machines produced by ASML, which have been essential for manufacturing the smallest and most powerful chips used globally. Since 2019, U.S.-led restrictions have limited China’s ability to import such equipment, creating a widening gap between Chinese chipmakers and industry leaders like TSMC.
For decades, the semiconductor industry has been guided by Moore’s Law, the principle that the number of transistors on a chip doubles roughly every two years, enabling continuous improvements in computing power. However, as physical limits to miniaturization become more difficult to overcome, Huawei is now promoting an alternative framework it calls the Tau Scaling Law.
At the center of this approach is a design method known as LogicFolding, which restructures how logic, memory, and analog circuits are arranged. Instead of relying solely on shrinking components, the technique stacks and tightly integrates chip layers to reduce the time it takes for signals to travel within and between circuits. Huawei claims this could improve efficiency, increase density, and enhance performance over the next decade.
Company executives argue that the semiconductor industry is approaching a physical limit to traditional scaling methods. According to Huawei Technologies semiconductor leadership, external restrictions have accelerated this challenge for the company compared to global peers, effectively forcing it to explore alternative technological paths earlier than others.
However, the proposal has sparked debate within the global chip industry. Some experts argue that the underlying principles behind LogicFolding are not entirely new, pointing out that techniques such as 3D chip stacking, heterogeneous integration, and advanced packaging have already been widely used by leading manufacturers.
Nvidia CEO NVIDIA Jensen Huang noted that advanced stacking and packaging technologies have been in use for nearly a decade, suggesting that Huawei’s approach may be an evolution rather than a fundamental breakthrough. He also emphasized that established industry leaders already have mature systems for high-performance chip integration.
Indeed, companies like TSMC have pioneered advanced packaging technologies such as SoIC, which enables multiple chiplets to be stacked and interconnected more efficiently to improve performance and reduce power consumption. Similarly, memory manufacturers including SK Hynix and Samsung Electronics have long used 3D stacking methods in producing high-performance memory components used in artificial intelligence systems.
Huawei, however, claims its LogicFolding approach could go further by dividing critical processing pathways across multiple tightly integrated layers, potentially improving speed and efficiency beyond current 3D integration methods.
Despite these claims, industry analysts remain cautious. Some warn that while stacking chips can increase density, it also raises thermal challenges, as higher power concentration can lead to overheating issues. Manufacturing complexity and yield rates could also present significant obstacles to large-scale production.
Another challenge lies in the broader semiconductor ecosystem. Huawei’s approach would require new electronic design automation tools, which are currently dominated by companies such as Cadence Design Systems and Synopsys. These tools are essential for designing and verifying advanced chips, and any shift in architecture would demand significant adaptation from the software side of the industry.
Huawei’s roadmap includes plans to introduce a new Kirin smartphone chip later this year, which is expected to be the first product based on its LogicFolding architecture. The company claims the design could improve power efficiency by more than 40% and increase peak performance by around 13% compared to previous versions.
However, independent verification of these claims remains limited. Analysts note that Huawei has not released detailed production data, cost comparisons, or benchmarking results against competing chips manufactured using more advanced process nodes. As a result, the industry remains uncertain about how the new design will perform under commercial-scale conditions.
If successful, Huawei’s approach could represent a significant shift in semiconductor design philosophy, particularly for regions facing constraints on access to advanced manufacturing equipment. But for now, experts say it remains unclear whether LogicFolding represents a genuine breakthrough or an incremental improvement built on existing technologies.
What is clear is that the global semiconductor race is entering a new phase, where innovation is no longer defined solely by shrinking transistors, but increasingly by how efficiently data moves within increasingly complex computing systems.
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