Lecture 08: Timing Arcs and Unateness

[Music] [Music] welcome to the course on blsi physical design with timing analysis in the this lecture we'll discuss about timing arcs and uness so the content of this lecture includes definition of the timing arcs then we'll discuss about the what is Source pin and a syn pin in a timing Arc then there are different types of oness like positive onet negative onet and non onet types of gates and what is the use of oness in a any kind of digital circuits and how it is used for timing analysis so first of all we'll discuss about the timing Arc so what is this timing Arc so it is basically uh defined as the it is uh defined as the relationship between two pins of a logic gate it can be this logic gate can be a combinational or a sequential so uh this uh timing Arc is also useful uh it is useful for it is useful for the St tool to do timing analysis and uh we have uh different types of timing Arc so it is divided uh into two parts so it is basically it is uh basically a part of the part of the timing part it is divided into uh basically uh two category two types one is called your cell Arc and the second one is called the Nate Arc okay so we'll discuss uh what is a cell Arc and a net Arc with an example okay so let's say I have a path here if you can see let's say it is a is a Norgate then we have a and gate then a buer so it's a mixture of gates are there then again again you have a exer gate like this so so which one is your cell Arc and which one is your net Arc so these uh Gates we can uh use different color this logic gates are basically your cell Arc so because this uh cell or logic gates are part of the timing path and this is these are called the cell arcs and we have net net means interconnect or a wi so these I can draw it in a different color so these are my Nate Arc okay so we need to consider both the cell arcs and uh the Nate arcs in the timing path so this is a timing path from input to the output we have a timing path so it consists of some cell Arc and some net Arc okay so this is the basic of your timing Arc okay now we'll go into now we'll go into what is Source pin and the syn pin h right sync pin okay so if you can see here one example I'll show you then uh I'll explain what is the source pin and syn pin let's say I have a gate here this is a nor gate followed by a n gate or you take a hand gate okay so let's say this is a pin this is B pin this is cpin okay this is let's say the gate one this is gate two okay and this is your output there are two outputs let's say we can this is o1 this is O2 okay so here if I can see you your uh basically your uh Gates so what are the source pin for gate G1 your B and C are the source pin and for uh and your O2 is the syn PIN okay so Source then the sink okay now for gate two your uh basically a and uh O2 are the Source pin and o1 is the syn PIN okay so this is the concept of uh Source pin and sync pin sync pin so now uh we'll discuss a few more examples in case of a uh I I'll ize few things in case of sale arcs okay okay so in case of sale arcs your input pins the input pins pins are Source pin and output pins are syn pin but in case of a net Arc in case of of Nate arcs the output pin of the uh so input pins of the cell input pins of cell here input pins of cell output pins of cell so here basically uh output pin of the cell output pin of cell are Source pin and uh input pin of the cells are sinkin okay for example if you can see here uh this is a net Ark okay this is the net Ark so the output pin is the so this is a net AR and the output pin is your Source pin and the input pin is your syn pin this is the input so this is a syn pin and this is the source pin for the N this is a source pin for nator this is a syn pin syn pin for net Ark similarly these are uh your uh Source pin for the sale uh Arc these are the source pin of these are the source pin of sell Arc and this is the SN pin of the cell Arc okay so this is the concept behind the source pin and the sync pin now we'll go into the uh details about uh uness what is oness okay what is oness so this oness is one of the important parameter for timing analysis and it is uh used by the St tool and we'll explain this with uh some analysis so basically each uh timing uh Arc has a timing sense actually each timing Arc has a timing sense so each timing arcs has a timing sense what is a timing sense is that it is denoted by un itness so what is this timing sense is that what it uh says that change in the output transition with respect to input transition that is called timing sense so this is used in case of static timing analysis so if you know how your input and output transitions are related then the timing analysis tool will pick the right delay value from the dot lips we'll discuss that in detail so now we have three types of on itness one is called positive onit what is this positive onet so if your input signal is uh Rising then your output signal is also Rising is uh rising or no change or we can say the input signal is uh falling and your output signal is falling or no change okay so we'll uh discuss uh this one with uh one example let's say take a case of a buffer so we have a buffer I have uh this uh this is the buffer so how many timing Arc is there you you have seen here if I your input is rising here okay output will also do a rise transition in case of a buffer so I have this is one Arc so if the this is first Arc this is the second Arc you if your input is falling if your input is falling then your output is also fall after a certain delay okay so this is your uh this is that's why it is called positive on it so input is rising output is rising input is falling output is falling so let's take a case of a and gate let's second uh second example and gate it is interesting why because it has multiple timing ARS okay it has multiple timing ARS for example I have a and gate okay it has two pin A and B the two input and get and your Y is your output so let's say your B is 1 B is fixed at one so input is rising then your output will also rise so this is one Arc okay so this is one Arc then the second one is let's say my input is falling b equal to 1 my output will fall so this is the second Arc then the third Arc is basically I have a let's say a equal to 1 and B is rising your output will also rise then the fourth Arc is a is 1 my input is falling my output will also fall this is a fourth Arc so all the cases your input is rising output is rising input is falling output is falling so that then there is another these four AR is actually used and there is another AR is also there but it is not used we'll explain why it is not used let's say one of the input is uh zero let's say B is zero okay so if I do a rise transition here your output will not change okay so here there was a condition that either rising or no change output is not change but it is not a Arc why it is not a Arc because if I put this gate with b equal to Z in a path then the signal will not propagate from input to the output in that path so it will stop there it will stop there the signal will stop there that's why this is not a so your and gate has four timing Arc similarly you can do it for a a equal to Z also those are not Arc because your signal will not further proceed in the path so so your and gate has four timing Arc now we discuss about the positive on it now we'll discuss about the negative on it so what is negative on it is that here the opposite so what is the opposite is that let's say your input signal is rising okay so your output signal is falling or no change your output signal is uh falling or no change okay similarly you can say input signal is uh input signal is falling means that output signal is rising or no change okay so here so let's say take an example of a inverter one example I'll take inverter which is having two uh Arc let the first Arc is let's say I have a inverter here let's say I'll do a rise transition in the input output will fall so this is a Arc timing Arc similarly the inverter it will fall then output will rise okay so inverter is negative on it because input is rising then the output is falling and input is falling then the output is rising and it has two timing Arc it has two timing Arc for a inverter now take an example of a n gate okay okay let's uh do it in the next slide so two input Nate so what is happening let's say I have a n gate is there I have n gate is there if my B input is one okay if my B input is one my let's say my other input is rising okay other input is rising your output y let's this is a output y will fall okay similarly if I have another case b = 1 and my input is input a is falling this is the then your y will do a rise transition so this is the second Arc similarly let's say your a is 1 and B is doing a the B pin is doing a rise transition your output will do a fall transition your a is one and B is doing a four fall transition then your output y will do a rise transition okay so these are the valid arcs okay you have four arcs but there is a Arc is there which is not valid because let's say if I do a nine gate okay if I do one of the input let's say your B is zero and a is doing a rise transition or fall transition together let's say I doing rise and fall transition okay your a is doing a rise and fall transition your Y is basically a b bar so B is zero means a into z bar so z bar is one so output will be held to PDD irrespective of change in the a input so even if you do Transition in the a input the signal will not pass to the next stage so it is not a valid Arc timing Arc so your two input nand gate has four timing Arc so now we discuss about the positive on it and and negative unet now we'll discuss about the non unet gate so non onet gate is such a gate it uh your output transition output rise and fall transition will not basically directly reflected on the input rise and fall transition it depends upon the what is the condition in the other pin we'll discuss this with one example so let's say you have a exer gate okay so what is the table of a exer gate so you have a b and Y both the inputs are same your output is zero and uh 0 1 1 1 1 0 1 1 1 0 okay so this is a exor gate so let's say you have a exer gate okay this is a exer gate okay so let's say my a is uh zero okay a is zero okay then B is doing a transition from 0 to 1 B pin is doing a transition from 0 to one what will happen to my y pin what will happen to my y pin so so initially b is z a is z output is zero okay and when B is changing from 0 to 1 so it will go to 1 you'll get rise transition so your input and output is behaving like a positive un it behaving like a positive on it if my a equal to Z let's say my I have another case I have exer gate this is your y this is a equal to 1 and B is doing a rise transition okay B is doing a rise transition so let's say your a is one a is 1 here and B is initially zero so your output will be 1 so now B changing from G 0 to 1 so now a is 1 B is 1 a is 1 and B is 1 so your output will change from 1 to zero output do a change from 1 to zero okay so here what is happening that it is a negative on it if my a input is is one okay so exer gate is a nonon type of gate okay exer gate is a nonon type of gate because your output transition will depend upon the state of the other input whether a is zero or one so based on that you cannot tell that a positive on it or you cannot tell that a negative on it when you do this uh uh get timing analysis in a path we have to know what is the condition in the other pin what is the condition of a pin or the B pin in case of transition happening in the a pin so this is an example of non onet gate so this is a DOT Li uh which is used for timing analysis so if you can see here this is uh timing sense whatever I was talking about how my output transition depends upon input transition so is defined here the timing sense which is a negative on it negative on it means that whenever you do a rise transition at the input output will do a fall transition and vice versa so this is a gate uh inverter uh basically this is inverter so here if you can see it has uh uh mentioned that for inverter the timing sense is negative minute so this is used in a timing analysis tool uh the timing analysis tool will check that it is a negative on it and based on that it will do the timing analysis based on that it will do the timing analysis so this is one of the use of uh uh basically negative on it so we discussed about the timing Arc of uh combinational circuits what about the sequential circuits so the timing ARS of ARS of sequential circuit okay so let's take an uh sequential circuit this is a deep flip flop so you have a clock pin so this is a clock this is a d pin or data pin then you have a Q then you some of the de flip flop as qar and you have uh asynchronous reset okay so if you can see here it has many timing Arc so for synchronous input okay so in case of synchronous input you have uh basically setup Arc setup check Arc okay so it has two variety rising and falling okay now we have uh hold Arc hold check Arc rising and falling then these are for the synchronous input okay so similarly you have uh asynchronous input basically your clock for synchronous input you are clocked to D okay you have setup check and the whole check so these are the ARs for setup check Arc from the clock pin to the dpin similarly for asynchronous input okay for asynchronous input what is the asynchronous input here your reset pin is as synchronous input so here we have two types of Arc is there recovery check Arc recovery check Arc the second one is removeal check Arc okay now you have third Arc is there which is called for the synchronous output okay so what are the synchronous output your q and Q Bar are the synchronous output so for that one you have one AR is there called clock to Q clock to Output propagation delay okay so that is also have rising and falling okay so these are the ARs basically involved in case of a sequential circuits these are the arcs used in case of a sequential circuits first of all we'll discuss about what is setup Arc and hold Arc so we have uh a flip flop and we have uh basically we have a flip flop it has a clock signal and it has a d pin and a q pin okay so now we can have basically first we'll plot the clock signal this is your clock then you have a data D which is coming before the rising age of the clock which is coming before the rising ede of the clock let's say it is going like this okay so what is the minimum time before the rising age of the clock your data should be stable that will be sampled by the plop properly that is your setup time okay so we are checking before the rising ede of the clock so this is your setup time similarly after the rising ede of the clock what is the minimum time I can keep the data stable such that it can be captured by the plop properly that is your whole time so this one this corresponds to setup Arc and this corresponds to hold AR okay so these two is very essential for checking the timing now we have uh one more component which is uh also with respect to synchronous output okay which is basically clock to Q propagation delay if your setup hold constraints are met properly you have a Q signal this Q which is the output of the flip Lop so let's say this is your clock signal your data may be anything before the rising age of the clock but since the data is satisfying your setup and hold requirement it will come after some time after the rising Ed of the clock so then this will be available at the output of the flip BL so this is basically your this distance is basically your clock to Q delay T clock to Q delay and this is basically clock to Q delay now we have one more uh Arc is there which is related to the asynchronous input reset we'll discuss that in detail so so what is a reset reset is a signal if you apply to the flip flop the output of the flip flop will be zero so I have my flip flop this is clock this is a dpin this is Q okay and we have a another another signal let's say here reset okay so in this case uh reset is active High reset is active High means that when reset is uh one means that your Q becomes zero irrespective of the whatever the data D applied to the flip flop so what is the situation here if I have any clock here let's say this is clock okay now I have a basically D input okay D input we changing like this then I have a reset I can apply the reset anywhere let's say it is active High okay this is active High here okay so now let's say I will apply here again so what is the point here is that so here I we are assuming that our reset is active high so here it is going from 0 to one so it is called assertion this process is called assertion and when it is going from 1 to zero is called D assess so here what is happening is that we have applied a reset and we have D input is there we have a reset is given to us then which will be basically driving the Q output so here the reset is applied or asserted so your Q will be zero after some time so here the Q uh can be anything before that okay it can be anything before that but after the reset is appearing so it will move from whatever the state to zero State once the reset is applied okay now again here it is again it will go to zero so this is the basically the meaning of assertion and de assertion assertion means that we are changing the reset from 0 to One D Ass means that we are changing the reset from 1 to zero okay where we are assuming that our reset is active high now with this background we are going to discuss what is uh recovery check R and removal check R recovery check Arc okay first we'll discuss the recovery check Arc in case of uh recovery Checker we are basically de asserting the reset signal and uh then we are uh giving control to the Flip Flop and flip flop should be driven by the D input instead of the reset input and one more thing is that what is the minimum time okay what is the minimum time required between the de assertion of the reset signal and the arrival of the clock signal such that the the new data can be captured by the plop that is your called your recovery time okay so what is the situation here I have a clock signal I have a clock signal this is my clock and I have a reset signal so it is active High okay so it is active high so it is changing here so then we have a data input D which is changing here okay now we have a Q which is the output of the flip flop so what is this minimum time before the rising age of the clock reset should be deasserted so what is the recovery check Arc is that what is the minimum time this time before the rising ede of the clock your reset signal should be deactivated or deasserted such that that your new data D can be captured by the flip flop in this age so that is your recovery time so in this Rising age your new data can be captured it will take some delay and it will appear at the output so this time is your recovery time this time is is your recovery time okay so this is all about recovery check AR now we'll discuss about the removal check AR so here we have a clock Ed we are drawing the clock first this is clock so now I'm drawing the uh reset signal so the reset is deasserted after the rising ede of the clock and whenever you are de asserting the uh reset how much minimum time after the rising age of the clock it should be deasserted the output will be zero output will be zero what is the minimum time my uh reset should be deasserted after the rising ede of the clock such that my Q should be zero so here if I have a data if I have a data like this then my Q will be changing and capturing the data in the next lockage in the next lockage so this time this time is called my removal time so in summary this is the minimum time after the rise in age of the clock the reset signal should be deasserted such that my Q is zero and it will act as a normal flip flop in the next Rising ede so basically here why we giving this minimum time here is that basically your Q output is driven by two inputs one is the reset input and the D input so there is a chance that both the things can create a meta stability inside the flip flop to avoid that we need some amount of minimum time after the rising age of the clock your reset signal should be stable such that your output will be reset Q should be zero so this is all about removal check AR so if you look into this uh uh dot LI or the uh timing Library this is the setup Rising uh timing uh type is set up rising and this this was the table for that one so this is this is giving an example of a set of rising Arc in case of a sequential circuit so how this uh tool requires this information to do the timing analysis in the complete path was stated here so the uh uness and timing arcs are essential for the timing analysis of any digital circuits so in this lecture we discussed about uh un nness Source pin and sync pin and different types of onet list like positive onet negative onet and non onet types of gates and we also discuss about the timing ARS of the sequential circuits so this is very useful for timing analysis of digital circuits thank you for your [Music] attention [Music] oh