Lecture 07 : Overview of Timing Analysis

[Music] [Music] welcome to the course on blsi physical design with timing analysis in in this lecture we'll do an overview of timing analysis and its application in vsi physical design so the content of uh this lecture includes uh the timing analysis how it is uh uh what is the meaning of timing analysis what is the significance of static timing analysis and uh we'll see how what is the use and where it is used inside a vsi physical design flow then there are two types of timing analysis one is called Static timing analysis one is called Dynamic timing analysis then then we have different types of path in a uh basically in our regular circuits so there are different types of path for example false path critical path and S path we'll discuss all of them with one examples so uh basically uh what is timing analysis so timing is one of the most important parameter of any blsi physical design or any blsi design in particular vsi physical design is intended for digital flow but any blsi design it may be digital or analog or mix signal always uh time uh plays a very crucial role we want to optimize the speed uh or we want to optimize the delay of the circuits to get get best performance out of it let's say if if we go to a market and we want to buy a smartphone okay so we want look for which is running very fast which has a very good processor inside it let's say we go to buy some laptop in the market we'll look for how many coures are there in the processor what is the speed of the course so the speed is one of the crucial factor which governs the uh basically the customers so so that the customers looks for Speed so as a designer we also look for how to maximize the speed of our design so it is possible there is a method to analy analyze it we need to have a method to analyze the speed of our circuits and that should be done at very fast manner okay so we have basically uh analyzes the timing of the circuits and optimize the speed of the design so the timing parameters of the circuits includes uh setup and hold time clock toq delay and we have rise propagation delay fall propagation delay all these into take into account to find out and uh find out those paths and optimize those paths so what is the significance of timing analysis it uh whenever you are doing uh timing analysis or static timing analysis what is the use of that it basically uh determines the longest path of of our design so whenever we uh talk about the speed that will be determined by the longest path in our design the longest path in the design is called the critical path okay so critical path of of our design so it uh usually people think that uh whenever we are looking for the speed we only uh look for the longest path of the design and it will reflect the speed of our design but uh if we do only that thing that is not enough for a chip design because sometimes what happens there are short path in the design which will basically are very important in terms of design point of view let's say we only analyze the critical path or the longest path in the design and we found found out the speed of the design and in the at the same time we do not did any analysis for the short path so it is not good good practice so we have to do analysis on the critical path or the longest path we have to do analysis for the short path or the minimum path the longest path is done to basically to avoid setup violation and the shortest path uh is determined to avoid hold violation so ideally the clock reaches to each of the flip flops at time T equals to zero but in general whenever you route the clock there is some kind of delay between them so that results in a clock skew that results in a clock skew let's say I have a flip-flop here I have another flip flop here both are connected by a age so ideally they reach at T equals to Z but in reality they don't reach at time T equals to Z because we have some interconnect length and also we have introduced some buffers in between we have introduced some buffer why the buffers are needed the buffers are needed to improve the transition time of the clock signal so the clock will rise sharply at the rise time so what is happening is that this buffer uh will add skew between the arrival time of the clock at node one and node two so that results into clock skew what is clock Jeter because of some random phenomena inside the uh inside uh the devices and uh inherent noises and substrate noise Supply noise all these things this clock arrival time may vary so that will also result in a clock gter these are non ideal parameters which also impact your design design timing so so we also need to do the timing analysis considering the clock skew and clock Jetter so there are another angle to the timing analysis that is called process variation so we have multiple Corners are there we'll discuss that in future uh slides but those Corners need to be analyzed properly in order to do the accurate timing analysis okay so we need to consider the process variations and their Corners uh into account while doing the timing analysis for a accurate prediction of the timing so this is the blsi physical day flow but uh uh in order to do the optimal timing closure at the end of the physical design we need to check the timing of uh the design at each St of the each stepe of your uh physical design flow so after practi partitioning after chip planning every step every step after partitioning again we have to check the run the St tool whether we are able to meet the timing or not after chip planning again we need to run the St tool to check that whether timing is met or not after the placement of the blocks again we need to check whether our required specification given to us has made or not and whenever we are going to the clock Tre synthesis because in in the initial logic synthesis phase we we assume that our clock tree is ideal but whenever we are doing clock tree synthesis there will be lot of buffer insertion and there will be lot of routing resources will be added in the clock tree then the clock skew and clock Jitter need to be considered so that will add to our timing so after the clock Tre synthesis we have to check the timing and if it is H again you go back and fix the timing and after the signal routing also we need to check the timing and check whether if it is meeting or not in case it is not meeting and again we go back and fix the timing in the we need to change the routing style so every phage of your physical design we need to check the uh timing whether it is met or not if it is not made then we will go back and uh do the modification uh and uh try to fix the timing then only at the last step we'll have to do less effort otherwise what will happen is that it will not be possible to meet the timing closure at the end of the vsi physical design cycle the timing analysis is basically divided into two category one is called Static timing analysis and the second one is called the dynamic timing analysis okay so the static timing analysis is uh uh basically is the timing analysis methodology at which we are we do the timing analysis of the circuit without applying any input vectors or monitoring the output of the uh without applying any input vectors and also we are not uh monitoring the output vectors so this was static static means that no input is supplied to the timing analysis tool so what is the process of static timing analysis we break the design into timing paths calculate the signal propagation delay along each path okay so we have uh multiple paths we break down down into smaller paths and find the timing propagation of each path then we check that actual timing constraint is satisfied or not okay if there is any kind of violation inside the design or input output interface if it is uh uh not met then again we need to modify the Z design and do the timing analysis again and again till we made the timing let's say I design a processor okay let's say the processor whatever I'm designing the speed of the design uh is basically uh for example is fixed at 1 GHz okay and the corresponding the the frequency is 1 GHz if clock is 1 GHz the corresponding time period P clock is is 1 nond so if my 1 nond clock is not met that one nond is supplied as a constraint in the timing analysis tool okay this one nanc is supplied as a constraint in the timing analysis tool then the tool will evaluate the actual critical path in the design and check that how much slag is there at the end if the slag is positive then my timing is met if the slag is negative my timing is not met then again we need to modify the design to make modify the design to meet the timing so this is a methodology was followed in case of static timing analysis what is daming dynamic timing analysis it verifies the functionality of the design by applying the input vectors and also it checks for the expected output at the output nodes and it also checks for uh whether the design is logically correct or not whether it is functionally working or not all these things is verified in case of dynamic timing analysis but it requires uh basically the simulation time required for dynamic timing analysis is more than static timing analysis as all the input UTS need to be checked okay all the inputs need to be checked so uh basically it is uh suitable for designs wherever we have critical components like the clocks crossing the multiple domains so where we are critical points are there there we need to follow the dynamic timing Dynamic timing analysis otherwise static timing analysis which is fast to determine the critical path that is uh basically employed in regular practice but in critical points we go for dynamic timing analysis so let's look into this uh total design you have inputs we have clock we have final output in between I have uh flip flops this is flip flop one this is flip flop two so if you can see here I have multiple paths in this design what are the paths there this is one path from input to to the D dpin of the flip flop one this is path one from input to the final output so this is path two so from here till here this is the path to through the combination logic then I have one more path between the flip flop one to the dpin of the Flip Flop 2 this is another path three then you have flipflop two to the output that is the path four so there there are several path inside a actual circuit so this is a example of different paths inside a actual circuits so there is also One path called clock path so this clock path uh is shown in a green line okay so these are different uh paths inside the timing pass inside the uh this particular example so if you can look into this one we have a circuit given in the left hand side and right hand side is basically a is a graph what type of graph we have already discussed several graphs are there this is basically called a directed a cyclic graph or d a g what is this D A each node to the other node there is some direction is there and that's why it is called directed graph some one each node to the other node there is a direction is there that's why it is called a directed graph and there is no cycle there inside the graph that's why it is called a cyclic graph okay so this is called directed ayli graph or D so if you can see here we have a source node and each of the inputs primary inputs these are the primary inputs i1 to I5 are the primary inputs o1 and O2 are the primary output these are the primary output okay and this is the directed acylic graph corresponding to these circuits so these uh circuits if you can see all the primary inputs and primary outputs are denoted by the vertices or the nodes and the connection between them are represented are as edges so when whenever you we uh talk about the timing paths it has multiple timing path inside this design from uh let's say from The Source node I can go like this like this like this this is my One path so there are multiple paths are there I'm giving you few examples of them so I can go by this uh I2 then G3 G2 G3 G5 and this one so there are multiple paths inside this the design so all the paths need to be analyzed by the St tool in order to find the worst case critical path inside the design so uh I have uh several paths are there critical path and the short path critical path is basically the path between the input and output with the maximum delay okay with the maximum delay the path between an input to the output with the minimum the S path but whatever I told you the critical part basically uh tells about the speed of her design and the short path is also essential to be analyzed by the timing analysis tool to avoid hold violation so there is another path called false path so we discussed about the critical path s path now I have a false path path uh the false path is basically a path that exist in a design which is not functional at any point of time but if you do not consider that path it may be shows as a critical path and it will uh basically give you a idea that your critical path is this false path is the as treated as a critical path however that path will never be activated at any point of time okay so that path will never be activated at any point of the time uh it is not required to meet uh the timing constraint in this path and uh because this design uh that path will not be activated at any point of the time so we need to find out those path in the design and treat tell the tools that this path should not be uh treated as critical path and Tool will uh Mark those path as the false path so let's take an example here so this circuit is given to you in the right hand side we have bunch of gates here Norgate inverter and multiplexer so the delay of the Norgate is 4 n delay of the multiplexor is three Nate is 1 nond so in this design we'll find out the critical path s uh shortest path and the false path in the given circuit so how do we do that we'll see what the paths exist here I have path one this is the path one uh this is the path one which is having a Norgate and a MOX DeLay So This is P1 then P2 is a Norgate multiplexor again Norgate and a multiplexor so this is P2 then I have a path three Norgate multiplexor and multiplexor this paths this is P3 now I have P4 is a not gate multiplexor and n gate like this this is P4 then P5 okay we have a not gate and uh one multiplexor and another Multiplex okay so this one is your P5 okay so I have five different path in this design okay five different paths in this design so which will be the critical which will be the false and which is the shortest path so now what we did did we found out the delay of each of the path the path one is 7 n path uh 2 is 14 nond path 3 is 10 nond then path 4 is 11 Nan path p is 7 nond okay which is the largest among them 14 is the largest but so these are the path and its corresponding delay 14 is the largest uh now we need to find out which is the critical path which is the shortest path and which is the false path in this design so if you can see here uh if you look uh look this circuits which is the longest path here it is the 14 okay but let's go into depth and analyze the circuit properly if let's say case one t equal to0 and this will be one so this is zero means this path will be selected okay okay and uh this is one means this is the path will be selected okay so if this is the case then what is the delay of this one delay is Norgate Norgate delay is four MO multiplexor is three and another multiplexor is three so it is 10 nond so this is 4 nond this is 3 nond and this is 3 nond total path delay is basically 10 nond now in case of case 2 when T = to 1 T equals to I'll write it in a different color this is one this is zero this is one means this path will be selected and this path will be selected like this this will come out like this okay so the delay of inverter is uh one this is 1 1 nond okay now the multiplexer is 3 nond now the n gate here it is 4 nond then you have this multiplexor is also one uh is 3 nond this is 3 nond so 3 3 uh 6 + 4 + 1 it is 11 n okay so uh this out of these two 11 is your critical path but if if I go back to uh 11 is the actual critical path in the design but uh in the previous case whenever we discussed that all the paths the 14 which is basically selecting both zero basically this path I'll uh do it in a different color this is uh okay so this path is a false path why this is a false path because this both cannot be zero at the same time because of this inverter okay and this path will never be excited or functional during the design of the circuits okay so during the design of the circuits this path cannot be activated because whenever s0 is z this will be one whenever s0 is one this is zero and both cannot be zero at the same time so in that case your this path is called your uh it is called a false path this is a false path so since it is a false path we need to tell the tools that we should not consider this path as a critical path so that it will not take into account while doing the uh critical path analysis then which is the shortest path here we have this P1 if I go to the previous slide this P1 and P5 so uh the P1 this path is shortest path and this path is the shortest part so both the parts are shortest uh in the design so both the things we need to be considered whenever you are doing the hold violation hold violation is not there because here we have not put any uh uh flip-flop here but if we consider this circuit as a combinational circuits let's say I have a uh flip flop here okay flip-flop one and I have this uh combinational design here then I have a flip flop two then this circuits is as a whole is representing this combination circuits then the s path for this design is 7 nond short path for this design is 7 nond which is used for checking the hold violation in this lecture we discussed about the importance of timing in vsi design and we can uh design we can uh analyze the circuits using static timing analysis and the static timing analysis is effic is essential at each step of your blsi physical design cycle and one more thing is that uh we need to check the timing at each step of our V physical design in order to meet the timing at the end of the blsi physical design and finally uh there are two types of timing analysis is there one is called Static timing analysis one is called Dynamic timing analysis static timing analysis is faster Dynamic timing analys is is slower but uh but whenever there is a critical Nets like clock domain Crossing multiple clock domain Crossing during that time Dynamic uh timing analysis is useful and we discuss about three uh timing paths there are three important timing paths like critical path s path and uh false path with one example thank you for your attention [Music] ha