[32] Ian Interviews： Pat Gelsinger, Intel CEO

One of the things you've presented today is the road to high NA with the integration into your roadmap. One of the comments recently have been about the economics of high NA, the financial economics, being able to bring it to market in a cost-effective way for customers who can use it. Simply put, do the economics of high NA work? Yeah, we're looking at it pretty carefully, of course, before I put that much capital at play, right, you know, in a high NA machine, a EUV machine, 250 million, a high NA machine, you know, 400-ish, right, so does do the economics work. And, you know, as we've looked at it pretty carefully, right, when you go to double patterning versus single patterning with high NA, yeah, we can make the economics work associated with it. Now, of course, you need to get the value of those tighter pitches that you're able to get, but we're looking at it pretty carefully, and we think it pencils out pretty well, you know, versus some of the other multi-pattern techniques and some of the self-alignment techniques that can be done. So, yeah, we think it's going to hang together. We're pretty excited about it. Of course, you know, with it, you have the field size, right, so then, you know, that becomes an issue if you want to, if you go to larger field sizes. So I'm challenging both ASML as well as my mass-making team, get me to bigger mass sizes so we can get that, you know, that field size back, right, and maybe even bigger mass sizes allow us to even get more economics in overall EUV overall. So a lot of pressure to make sure the economics work, because one of the things was, you know, as we move through the EUV generation, the economics of Moore's Law stopped. I have to get the economics back into Moore's Law as well, so it's not just building faster transistors, lower power transistors, but cheaper transistors as well, and that's a big priority for us, is make sure the economics are in the Moore's Law on the other side of the EUV transition. So that's even with the, say, increased ASPs of some of these more advanced packaging techniques, because those sort of products will be on the bleeding edge. They will be the ones that are powering, you know, the big machine learning clusters, so the economics of making a cheaper transistor yet in a more expensive product. Yeah, and, you know, fundamentally to me, it's always, is it economically, you know, because Moore's Law was a technology statement, but even more so it was an economic statement, and if I can build products that are faster, less power, and cheaper, okay, everybody got to go there. You know, that is the magic of Moore's Law, and when you don't have the economics there, then it's sort of like, if I stay on the current node, right, I can be more parallel. A lot of these AI machines, you know, go slower and more parallel, you know, to get their performance capabilities, and if I say, hey, you got to move to the most advanced nodes because you get power, performance, and cost, okay, then it's a killer value proposition, and we are in the heydays of the next phase of Moore's Law, and frankly, I believe we're there. I think we're going to make that work. So you've said today that you want to be the number two foundry by 2030, and yet the rest of the presentation is about how you're a different foundry than everyone else, this whole concept of systems foundry. What I wanted to ask you is, is that number two comment about revenue, wafers, performance of end products, what's the best metric to go about there, and how far are you along that line already? Yeah, and explain in the statement a little bit, you know, I'm probably already the number two foundry in the world if you count internal wafers. So are you when you say that statement today? So when I say by 2030, you know, what I mean is in terms of external foundry. Okay. Right, so just, you know, so that is a very substantive statement because we're saying we're going to be by revenue the number two foundry by the end of the decade, you know, that's the goal I've set out for our team, and that's above the revenue that I get from the internal foundry business. So the combination of those two, well, I believe it's going to be a big number by the end of the decade, but we're trying to be very transparent, and I'll say appropriately comparable, my external foundry will be number two in the industry. Obviously, we expect TSMC to be number one, and we expect by then we'll have passed Global Foundries, UMC, Samsung as the number two revenue foundry in the world. Are you including packaging in that revenue? Some of it will be advanced packaging, right, as well. And by the way, TSMC does the same thing as well, so we think that's a fair compare. And we do think that advanced packaging will be, you know, well below 50 percent, but it's going to be a growing piece of the revenue. And when you think about advanced packaging, Ian, is it wafers or is it packaging? And increasingly, advanced packaging is wafer technologies, you know, wafer level assembly techniques, you know, hybrid bonding, you know, you're going on to silicon-based substrates. So is that more silicon wafers or is that more packaging? It might end up being glass. And over time, it will be. So with that, you know, we think that's a fair comparison, right, of saying the advanced packaging is one of the elements. So relationships like UMC and Tower will give us some legacy nodes, right? We'll have advanced packaging, but the majority of that revenue will be, you know, leadership post-EUV wafer revenue. One of the big drivers in the chip market right now is your competitor, TSMC's COOS availability and their ability to supply. You've extensively spoken about EMIB and Foveros and then leading into Foveros Direct. However, what would you say is the comparative competitive technology Intel has against COOS? Well, Foveros and COOS are pretty comparable, right? Right. A little bit different. And clearly, due to some of the supply limitations that you described, you know, some of our advanced packaging customers today are essentially taking Foveros and we're helping them to be able to move their COOS designs to Foveros. And it's just driven by supply chain today. And hey, you have advanced packaging capabilities. We can do Foveros with you. You know, this gives us more volume of our AI chips. Most of these are AI customers. So it's just what I've called the fast on-ramp, you know, into the foundry business. But now that we start to work with them, we explain, well, you know, COOS and Foveros, you know, are square functions, right? You're scaling both in the X and the Y, and that's a pretty expensive base die. If we use EMIB for high performance bridged connection, you know, for some of that, that's way more cost effective in a lot of circumstances. And customers are now starting to look at our packaging, you know, technologies to sort of say, wow, so I could use some for EMIB and some with Foveros, right? And get a more economic and high performance design. And they're sort of saying, well, that's pretty interesting. And then they're starting to see some of the advanced testing capabilities that we provide, you know, which also when you're bringing many of these components together onto a advanced package, you know, all of a sudden the individual die or chiplet, the testing associated with that becomes very critical in the overall, you know, yielded cost structure of the full complex advanced package. So we do full performance singulated die testing. Oh, another differentiated capability. And then we tell them about Foveros Direct. Oh man, now I can actually do full die on die 3D assembly. So I'm now innovating an X, Y and Z dimension, right? And I'm able to pick which transistors I move to the most advanced node versus which ones like analog or cache cells might be better on a node or two behind, you know, and be able to put those together with full, you know, sub 10 micron, you know, bump pitch technologies. These are pretty exciting capabilities. So we expect this to be a pretty meaningful on-ramp for our overall Foundry customers that not only are we a second supplier, but we become their best supplier. Okay, so is Foveros Direct going to be a chip on wafer or a wafer on wafer technology? It's a, you know, chiplet on chip technology, right? Now we're working on, you know, ideas where actually you don't need, you know, right now the base die needs to be bigger than the composite of the chiplets that are put onto it. Now we talk about some of the EMIB Foveros Direct combinations, right, which allow those to not be necessarily, you know, aligned. Foveros Omni. Yeah, Foveros Omni, where you can actually have different dimensionality and use of EMIB and Foveros Direct in one advanced packaging. So then truly you have, you know, I'll say complete flexibility of the dimensions of the base die and the top die and how you interface those. So that gets to be, you know, then the design palette gets to be pretty big. Yeah, nice and simple. So one of the questions I get often, at least when you announced this, you know, IDM 2.0 strategy, is the, and I'm sure you had a ton of questions about does this mean that Foundry will become its own entity and the split, because we saw obviously what happened with AMD and Global Foundries. Some of that has subsided coming back in, I think, with what you've been able to demonstrate up to today, but there's still like a core contingent of, you know, what if an investor tries to force a split? That's not the question I want to ask, but the question I do want to ask is how are you keeping your product teams and your manufacturing and technology development teams the best of friends? Yeah, and part of that is, as I said in the keynote this morning, I need to make them independent, right? You know, build the best products, build the best wafer and package technologies, and we're formalizing the interface between them like a foundry. You know, here's the price list, this is going to, you know, create better cost dynamics, you know, better engineering disciplines, you know, by creating that. I'm giving the product group some flexibility to use external foundries and the foundry group, you know, the mandate to go win external foundry customers as well, but at the same time they both work for me, right? And the only way that I fill those factories this decade is by Intel product wafers, right? The economics won't work, the scale doesn't work without keeping that interdependence of the two entities, you know, and this is many decades of experience as we're rebuilding, you know, the strength of the technology and, you know, frankly the strength of the engineering teams on both sides, you know, both of them are moving up that maturity curve, right, in this and so, you know, I get to be judge and jury on some of these decisions to make sure we stay on track. Now over time, I expect they're both going to have more autonomy to make those decisions independently, but in this period of rebuilding the entity, this is super important that I keep them working effectively together and, you know, I spend time on this probably almost every single day, you know, making sure that we're building more independently maturity, but we also maintain the value of that interdependence on a daily basis, but it also works for both customers. Let me give you, you know, a quick example, Ian. The external foundry customers that I go to, right, I talk to them and I say, I've already committed all the Intel revenue to this process technology, right, and they say, well, should I trust that it's going to work? I've already committed tens of billions of revenue, you know, I am pushing those factories down the economic, the defect densities, the process maturity, your risk of considering those is substantially reduced because I'm already committing it. I am debugging, I am making them yield well to support the Intel business and they go, that's a good point, you know, that lowers the risk of me creating the supply chain with you. Now in the other direction, you know, the product teams sort of say, well, they're not just servicing me anymore, right, in the foundry side. It's like, that's right, but now they will essentially work with the entire industry because any new technology, you bore 100% of the brunt of getting that technology mature. Now the entire industry is creating a richer technology base for the product groups to choose from because, you know, if one of the product groups says, I'm not ready for hybrid bonding and Phobos Direct, it's sat on the shelf, right. Now we have the entire industry to innovate from and as a result, a richer set of technologies for the product groups to choose from that are already matured by somebody other than them in the industry. It actually makes both sides of the business better. Both of them must become more competitive, more cost efficient, but also better technologists as well. So, I mean, that's an avenue we could go down for hours. Unfortunately, my time with you is limited. With this engagement with UMC, for Intel 12, or is there an official name for it yet? Yeah, Intel 12. Yeah, it'll be UMC 12 and it'll be Intel 12. Both of us the same, you know, the same technology. Okay, so why did you need to bring UMC in? What did they have that Intel didn't? Because you have all the equipment, you have experience with 14 and 10. Yes, they were custom tools and they needed to be more open. There's a bit of, I think, misunderstanding about why even involve UMC at all. Why couldn't you have done a PDK yourself? We could have and I don't think we would have learned nearly as much as we're going to do through this partnership with UMC because they know how to, you know, create and support these customers. You know, they have a rich set of customers that want to move on to this node, you know, that they've been working on and they're 16 and they're 22 and so on that want to move forward, you know, to this node. But they also know how to not just do one PDK but to do many PDKs. The PDK for high voltage, for RF, for analog purposes, you know, for power delivery purposes and so on. You know, they've perfected how not to get 12 done but to get the portfolio of 12 done. Intel doesn't do that. You know, we essentially did one process node for essentially one class of design, that being high performance leadership compute. You know, they've mastered how to make multiple nodes off of one core investment. So we believe this is a great investment for them because they're going to be expanding their supply base, right, a factory that I'm going to have well capitalized, right, and be able to bring some level of new equipment into that to deliver 12. But mostly it's on a factory that I've already built and I'm running. You know, they're going to be able to go to their customers and saying we have a more resilient supply chain. You know, we have a U.S. supply chain, you know, as well as an Asian supply chain. So it's good for their customers. They already have customers that are anxious for this node. You know, we've gotten great response, you know, from some of their customers saying, you know, I'm ready to move major design volume to this as well. And I think we're going to be able to take this factory, we're going to learn a lot through the process as well. You know, and what if I put my best people working on a 12 nanometer node? I think they have talent and expertise here that's just going to complement, you know, the Intel factories. I'm really quite excited about the partnership, super excited that Jason's here, you know, and I think this is going to be a winner for both of us. It's been said in the past that Intel bets the whole company on the next process node. Is that still true? I've bet the whole company on 18A, you know, and hey, you know, we have committed products to this, you know, it is the culmination of our five nodes in four years, you know, bringing that across the line. So in that sense, yeah, I've bet the whole company on making this successful. Now, going forward, of course, we expect that, you know, we're not quite as unidimensional as the question would imply, you know, as we're building more Intel 3 variants, we're going to have 18A variants, we have tower and UMC as mature nodes, we're going to have a portfolio advanced packaging, you know, customers and partners as well. I really do want the customer to become more multi-threaded, right, in terms of its revenue and technology base right now. But yeah, I bet the company on making 18A successful. Being given the hurry up, so one last very short question. You've said you wanted to, you know, regain leadership by end of 2025. Is that foundry? Is that product? Is that both? Both, right, and we believe with 18A, it's the best transistors, backside power, you know, and some of the evidences that were described today by some of the EDA and IP providers, they're getting the best performance, the best area, best power, you know, results from 18A. So, you know, it's the best process technology, and then we're taking our products, and I am pushing our products onto the leading edge of that, you know, Clearwater Forest, our next generation server part for 25, you know, we already have that in fab now, Panther Lake, our 2025 client product is already in fab at this point, you know, so we are pushing the envelope to leverage those process technologies and packaging technologies to build again the best client and server products as well. So yeah, we are on path to be back to leadership with process technology, with our foundry offerings that we present to customers and the best products in the industry. That's the path that we've laid out, and everything is coming together. And as I said in the keynote today, hey, we're not done with this arduous trek that we set for the company of five nodes and four years and rebuilding our execution machine, but today was a pretty profound day, opening the doors up, and we see the light at the end of that very challenging trek, and we laid out what's next, you know, 14A, the new process variants, you know, a cadence of technologies, and we got great industry resonance that yes, in fact, this whole picture is coming true. Awesome. Well, thank you very much. Thank you. Good luck. So, you know, a fun little story. You'll appreciate this, Ian. So when I was designing the 8386, I wanted to put built-in self-test into it. Right. Right. But then the question is, you know, because then that's before you have any of these big fancy packages that have lots of IO, you know, you're putting this into, you know, 48 pin or 60 pin, you know, packages. So IO was at a huge premium. So the idea was how can you actually build very efficient, you know, testing mechanisms into the chip? And it turns out that linear feedback shift registers was one of the most efficient ways to build, you know, circuits that both could generate patterns as well as detect, you know, with high probability, you know, errors and pattern, you know, so it ended up being a great way to collect failures, right, or failure patterns as well. But it turns out that the world's most advanced linear feedback shift register work was done by Russians. So I had a friend of mine translate the Russian LFSR papers right into English for me then to create a program that ran the LFSR code that was done by these Russian scientists to make sure it worked, right, you know, to make sure it worked and that I, because, you know, the thing was that I was doing, you know, 36 bit and 32 bit and 37 bit, you know, I needed different size LFSR registers. And as I'm reading the papers at the, you know, halfway through the paper, right, it says, this is what we do to manually calculate these over weekends, right. And in the middle of it is, this is a good time for a vodka break. You enjoy people who put in the fun stuff into papers as well. So anyway, that was pretty geeky. So yeah.