Meet the Founders Using AI to Build the Next Generation of Chips

We're here with Azalia Mir-Hosseini and Anna Goldie. They are founders of Recursive Intelligence. Thank you so much for being here. Really appreciate it. Thanks for having us. Yeah, of course. So tell us a little bit about the company and what it does and why everyone's getting so excited about it. We are building a platform for chip design as our first product. Thank you very much. So... We think of chip design as a complex multi-stage process that AI and computational algorithms are very well suited to take care of. And what we are developing is this end-to-end automated approach to chip design from architectural exploration, model hardware software co-design, all the way to GDS and silicon. The way we are approaching this, like I said in the panel earlier, is that we are enabling scaling laws for hardware design. Our algorithms scale with compute. They learn as we solve more and more problems. They gain experience. And what this enables us is that not only we do every stage a lot faster, and we are talking about orders of magnitude faster, we can also co-design across these various stages of chip design From front-end to verification all the way to back-end optimization and that is something that unlocks a whole new way of approaching chip design and hardware. Yeah, it seems like it really does unlock an entire new world here if you're having AI design the chips that then power AI. So it's a pretty exciting space to be in and something that, again, seems so unique and so important, especially with that speed. So talk to us about how your company and how this process could really affect the speed of all AI moving forward. So we think that chips are the fuel for AI, that the more compute you apply to pre-training a model, the more intelligence you get, the more you apply at test time scaling, the more intelligence you get. So we believe that by using AI to quickly design chips that are custom to particular AI models, we can get more effective compute, more intelligence, and do so faster than was ever possible before. And we've developed algorithms that are a thousand X faster than previous approaches for key stages of chip design. Yeah, I mean, it's just incredible to think about the speed that you guys are able to get with that. Tell us what you think that will kind of translate into then if we're talking about so much speed and so much faster development. What do you think this is going to look like then in, I don't know, just by the end of this year, by two years, 10 years? Cheers. So on the development side, again, we are translating compute to faster timeline to make the chips and better chips. And what that means is that we can make more variety of chips. We can customize them to the workload so we can get more performance. We can enable new applications. We can also, like Anna mentioned, we can get more, we can create more intelligence out Any given amount of compute energy, wafer size, and all of that that we put into an existing chip by doing this customization, which is, again, empowered by our faster iteration loop because if we customize chips, they better be out in the market very fast so they can be relevant and useful. Yeah, it's so important to get it out there while you're still then working on the next thing down the line. When it comes to actually building these chips though and building AI that's building the chips, talk to us about some of the challenges that you face with that because this does not sound, especially from my point of view, like a simple process. So tell us a little bit about some of the challenges that you face. I mean, chip design is extremely complex and there's multiple stages, as Azalea is mentioning. So For example, on the back end, you have to figure out how do you place hundreds of millions or even billions of these gates onto these multiple wafer layers and route wire each and every one of them, subject to many different physical constraints. So it's an extremely complex problem. But fortunately, we've developed new AI approaches that can do this really, really fast. So that part is good. I think design verification is another key challenge in chip design. So it's ensuring that the chip is actually correct. So in software, you know, if you have bugs, You can fix them, right? You can apply a patch. With a chip, if you manufacture it at massive scale and there's a bug in the chip, you may be out hundreds of millions of dollars. And it's very difficult to fix post-facto. So design verification is the process of trying to determine in advance whether there's any bugs in that chip. And previous, like, prior approaches are, like, say, dynamic verifications, checking every possible state of the chip in every possible sequence to determine if it ever was in a state that you didn't expect, or formally proving that the chip is correct mathematically, and at the scale and complexity of modern chips, that's extremely challenging. But we see ways to do that. Well, I was going to say, it sounds extremely challenging, but also incredible that you guys are able to kind of pool your joint knowledge and come together to make this happen. You guys both have incredibly impressive backgrounds. Talk to us a little bit about how the backgrounds that you have and the experience you have has really helped in this. Because again, this is not simple. And you guys are solving a really incredibly complex problem here. I think from my background, I studied computer science and linguistics at MIT, so my goal was to work on language models, and then I did my master's there in EECS, and then my PhD at Stanford in reinforcement learning. Azalea is actually a professor of CS at Stanford, and yeah, we worked together. We worked together since 2016, we joined Google Brain Team on the same day, and we started a team together on machine learning for systems, the mandate of the team was to create AI algorithms that can solve problems and optimization problems across the computing systems, such as compilers, distributed system management, and chip design, and AlphaChip is perhaps the work that got the most attention. And this was this RL agent that could do chip layout optimization, and it was very new back then. RL was not a prominent approach back then. It was using AlphaGo successfully, but to a real engineering task, especially as hard as it gets and complex as it gets in chip design, it was a very fulfilling experience. It was a great experience. And it took us some time to convince our chip design colleagues at Google to work with us, adopt our techniques. But then just like AI enters any field, once it starts showing the improvements, it just keeps getting better and better over time. And now it's been used, I think, five generations of TPUs, Axion TPUs, Pixel phones, Waymo chips, external adoption by MediaTek. So to us, that's the most exciting. Better than being published in Nature, right? Yeah, no, it's absolutely incredible to think about what you've done and what you'll also continue to do. Thank you so much for being here today. We really appreciate it. Thank you.