Lecutre 16 Module 01

This is lecture 16. So, in the previous lecture we were looking into the architecture of a common source amplifier where we used capacitors in place of to replace the multiple batteries that are required in order to bias the transistor and apply the voltage, apply the incremental voltage simultaneously and the architecture that we ended up with was the following. So, note that we have only one voltage source VDD, the bias at the gate of the transistor is being derived from the resistor divider network formed by the resistors R1 and R2 and note that at the gate of the MOSFET no current is getting diverted, no DC current is flowing this side or that side, there is absolutely no DC current because in both sides one side I see a capacitor which is open at DC on the other side I also see kind of a capacitance of the MOSFET which is again open at DC which means that I do not have to worry about loading, right. So, nicely my R1 and R2 network will be able to provide the appropriate bias for the transistor. How are we and then we saw that we needed to apply, we needed to apply a DC, we needed to apply the incremental input also and needed to ensure that the gate of the transistor has swings with the entire almost entire incremental input. So, for that what we needed, we needed a, we needed a battery, we needed a battery between the gate of the MOSFET and the input source. So, what was the role of the battery? The series battery was supposed to, was supposed to give us a lift in voltage, right. So, then we saw that a series battery, we cannot use a battery in series because of multiple reasons, then we made the observation that a sufficiently large capacitor can act as a battery. Initially, we noticed that an infinite value of capacitor will do the job. So we put C1 to be equal to infinity and we coupled the input Vi and Rs and by the way this type of coupling, the input from one side of the capacitor plate to the other side is essentially is also called AC coupling, right. Very often if you talk to circuit design professionals, they will sometimes say why do not do AC couple your input, when one says why do not do AC couple your input, it is implied that you understand that there is probably a coupling capacitor which is being used to, which is being used to store a different DC voltages on either plates. However, the role of the capacitor is to pass the input, pass the incremental input as and when it appears it one of the places. So, this is what exactly this capacitor C1 is doing. So, the C1 is holding on to a DC voltage of VDD times R2 by R1 plus R2, but also if C1 is large enough, it is not storing any AC voltage across it, right. It is not storing any incremental voltage across it because if infinitely large capacitor essentially acts as a short circuit, right. Then we notice that, I mean how long can we, theoretically we can deal with infinitely large capacitance, but ultimately we are circuit designers, we will have to make circuits and you cannot get a capacitor with infinitely large value. So, we needed to figure out what is the constraint on the capacitor so that I can use a finite value of capacitance and yet mimic the role of an infinite capacitor. Then we saw that one way to approach it is to, we saw multiple ways of approaching it, but it seems like the time constant method of approaching it is the most intuitive one. What was the time constant method of approaching? The time constant method of approaching it was, if this is a first order network, all we need to ensure that the time constant associated with the capacitance is much, much larger, right, than 1 over omega, right, so this was where omega was the frequency of interest. So, this was essentially the crux of, I mean one major outcome of the previous lecture. Then we shifted our focus to the output side and again we saw that there was a constraint that RL is, the load RL need not necessarily be a explicitly defined resistive load where you have access to both the terminals, the RL can be an implicit load of a next stage where you probably had only access to one terminal and the other terminal is probably implicit ground or maybe something else. So, since you have only access to one terminal, you cannot put that RL between the drain of the MOSFET and the source and the power supply, so that job has to be done by a separate resistor RD and we again AC coupled, we again AC coupled the value, the resistance RL. When I say AC coupled, why did we need to AC coupled? We needed to AC coupled because the quiescent voltage across a resistor which is grounded at one side is 0, however the quiescent voltage at the drain of the MOSFET is a finite value. Now if I connect these two together, obviously the resistance RL will draw DC current, in other words the resistance RL will load the network, we did not want it to load, what was the one way of fixing that? One way of fixing that is to lift the quiescent voltage of across, I will leave the quiescent voltage on one, I mean one way to fix that was to make sure that the quiescent voltage on both the sides like the MOSFET side on the resistor side are identical, one way to do that was to put again a series battery across, I mean in series with the resistor such that the value of the battery is exactly equal to the quiescent voltage of the MOSFET, at the drain of the MOSFET. Then again we saw, we know that putting a series battery is not possible, but by now we already know that there is a solution, what is the solution, put a very large value of capacitance. So, we say that we will put a very large value of capacitance, arguably an infinite value of capacitance and then we will want to figure out and then we saw that this probably gives us what we, what we want, right. So, now when we stop, we did not evaluate what will be the constraint on the value of C 2, right. So, now in this lecture, at least at the beginning of this lecture, I would like to evaluate what is this, what is the constraint on C 2, because like C 1, I cannot assume C 2 to be infinitely large, right. So, what is one way of going about it? The most obvious way of going about it is to write the entire transfer function and then see what is the constraint in C 2 such that the drop across C 2 is negligible, right. So, what do we want? We want under AC circumstances when the signal is swinging, this entire contraption should behave like as if the capacitors were not there in the network in the first place, right. So, if I, if we, if we sketch the incremental equivalent of this network, what will we get? We will get this is V i, this is R s and let us assume that C 1 is large enough to be treated as a short circuit, right. If C 1 is large enough to be treated as a short circuit, this becomes R 1 parallel R 2, right, because V dd is grounded, incrementally V dd is grounded. So, this voltage is V g. What should I replace the MOSFET by? What is the, assuming that the MOSFET is biased in saturation, what is the incremental equivalent of the MOSFET? The incremental equivalent of a MOSFET is only g m times V gs. What is the source? Source is grounded. So, essentially this becomes g m times V g. What happens to register R d? This remains as is. The top of the register is grounded because a DC voltage source V dd in an incremental model is grounded. Then what happens here? We have this capacitor C 2 and we have the resistance R L. So, and, and, and V naught is the voltage across R L that we are interested in. So, what is V naught over V i? So, what do we need in order to figure out V naught over V i? In order to figure out V naught over V i, we need to know what is the value of this current because this is the current that is flowing into, part of this current is flowing into R L to, to, to, to develop that voltage V i. So, what, what does this voltage depend on? This voltage clearly depends on V g, right, this voltage depends on V g. So, what is V g? V g is nothing but V i times R 1 parallel R 2 by R s plus R 1 parallel R 2, right? And if, if you go back to lecture 15, what did we, what comment did we make on sizing these values of R 1 and R 2? We made the comment that we understood that we would want the entire signal to, to appear at V g, right? Why do we want that? We want the entire signal to appear at V g simply because you would want maximum gain. We want Y 11 of this entire contraction to be 0, which means that we do not want this R 1 parallel R 2 to load our, load the input source, right? So, if, if R 1 parallel R 2 is much, much greater than R s, V g becomes, approximately becomes equal to V i, ok, ok. So, if V g becomes V i, what happens to, so let me, let me copy this. So, V g is approximately equal to V i, right? So, now the focus shifts completely to the, to the output side, right? This is the drain, this is the V d. So, what is the, what, what is the voltage across R L? So, clearly this part of this current, part of this current g m V g flows into, into R, into, I mean the current gets divided at the node V d, right? So, g m V g comes at, so my, g m V g is flowing downwards. So, if I say, if I want to argue from the perspective of what is the current flowing upwards, then minus g m V g is flowing upwards. So, minus g m V g arrives at the node V d and part of it has to go right and part of it has to go top, right? So, what part of it will go to the right? So, clearly the, we know this is, this is like an impedance divider. So, so this part that will go to the right that is I naught, let us say this is I naught, this will be minus g m V g times R d over R d plus 1 over S c 2 or rather 1 over j omega naught c 2 plus R L, ok? So, now from there, from here what can we, what will we, what constraint on c 2 do we get? Clearly, we see that if c 2 has to behave like an infinite capacitor, then 1 over j omega naught c 2 mod of this has to be much much less than R d plus R L, right? So, if c 2 were infinite, then the denominator would simply have been R d plus R L, right? So, we are trying to figure out what is the constraint on c 2, so that it behaves almost like an infinite capacitor, which means the constraint on c 2 becomes c 2 should be much much greater than 1 over omega naught R d plus R L, right? This is pretty straightforward, you do, you basically follow KCL and you do the algebraic manipulation and you arrive at that, right? However, we know a more easier way of arriving at the same result. We discussed this in the previous lecture and what was the discussion about? The discussion was from the perspective of time constant. It is not always easy or it is not always intuitive to write out the full-blown transfer function and then try to figure out what will be the constraint on various capacitances. In fact, I mean, if you want to do that, you can do that in principle and you will get a good closed form solutions, but sometimes it becomes too exhaustive a analysis. So, engineers found out multiple ways of reducing the analysis analytical burden on our mind, right? So, one of the ways of dealing with first order networks is to look at the time constant of the network and coming to conclusions and we saw that in the lecture 15 and what did we see? We saw that if we look at only the time constant of the network or if we need to figure out a constraint on the value of certain capacitance, all we need to do is to find out what is the Thevenin impedance the capacitor is seeing, right? If I sit on the capacitor and I see what the Thevenin impedance it is seeing, then I will be good, right? So, what is the Thevenin impedance or Thevenin resistance in this case across C2, what will you do? Firstly moment I asked you to find or anybody asked you to find resistance or output resistance impedance or whatever, then the first thing to do is to desensitize all sources. So, in this case V1 goes to 0, so V1 goes to 0 means this gets shorted, so let me also short all the grounds together because it gives a good visual representation of what is actually happening, ok fine. So, if the input is shorted, what comment can you make on the voltage Vg, Vg clearly is equal to 0, if Vg is equal to 0 what comment can you make on the control current source gm Vg, this clearly goes to 0, in other words that does not exist. If it does not exist, what do you see? You see only what is remaining, the only stuff that is remaining is this loop, correct, the only stuff that is remaining is this loop, ok. So, what is the and if you are sitting, if you are trying to figure out what is the Thevenin impedance looking on both sides of the, looking from the capacitance, what are you essentially saying? I am saying that this is the port, so this is the port across which I am trying to measure the resistance and how do you measure a resistance? You apply a test voltage V test, so you apply, let us say I apply a test voltage V test and I find out what the test current is, in this case clearly the test current will be V test over Rd plus Rl, right. So, this test current I test will be equal to V test over Rd plus Rl, so in other words, in other words R Thevenin will be V test over I test which will be equal to Rd plus Rl, which means what? Which essentially means that the time constant tau is C 2, time constant tau associated with C 2, right, time constant tau associated with C 2 which is tau 2, let us say is equal to Rd plus Rl times C 2, right and if you want the capacitor to act as a short circuit which means you want the capacitor to be large enough, what is the constraint? The constraint is this time constant has to be much much greater than 1 over the frequency of interest, right or in other words you would want, you would want any, a signal at a frequency omega naught to pass through the capacitor without seeing any voltage drop or in other words you would like the capacitor to act as a short circuit as a frequency of interest, right. So, which essentially means that you get the constraint C 2, C 2 should be much much greater than 1 over omega naught Rd plus Rl, right, note that we have come to the same conclusion using both analysis, the reason I have, I am doing this multiple analysis repeatedly at this stage of this course is because I am trying to, I am trying to give you an idea that it does not matter from which direction you approach the problem, you will essentially get the same answer. Going forward what we will do, I will drop the transfer function analysis in order to figure out what the capacitances are, I will resort to only time constant based analysis because as we will see as a circuit gets more and more involved, it is much easier to figure out what the time constants are rather than trying to, trying to put together the entire transfer function all the time, ok.